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september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion mcp data sheet tm
ds05-50306-1e fujitsu semiconductor data sheet stacked mcp (multi-chip package) flash memory & sram cmos 16m ( 8 / 16) flash memory & 2m ( 8 / 16) static ram mb84vd2108xem -70 /mb84vd2109xem -70 n features ? power supply voltage of 2.7 v to 3.3 v ? high performance 70 ns maximum access time (flash) 70 ns maximum access time (sram) ? operating temperature C40 c to +85 c ? package 56-ball bga (continued) n product line up note: both v cc f and v cc s must be in recommended operation range when either part is being accessed. n pac k ag e part no. mb84vd2108xem/mb84vd2109xem supply voltage(v) v cc f= 3.0 v v cc s= 3.0 v max address access time (ns) 70 70 max ce access time (ns) 70 70 max oe access time (ns) 30 35 56-ball plastic bga (bga-56p-m02) +0.3 v C0.3 v +0.3 v C0.3 v
mb84vd2108xem/2109xem -70 2 (continued) flash memory ? simultaneous read/write operations (dual bank) miltiple devices available with different bank sizes (please refer to ordering information) host system can program or erase in one bank, then immediately and simultaneously read from the other bank zero latency between read and write operations read-while-erase read-while-program ? minimum 100,000 write/erase cycles ? sector erase architecture eight 4 k words and thirty one 32 k words. any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture mb84vd2108xem: top sector mb84vd2109xem: bottom sector ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready-busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ? low v cc write inhibit 2.5 v ? hiddenrom region 64k byte of hiddenrom, accessible through a new hiddenrom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? wp /acc input pin at v il , allows protection of boot sectors, regardless of sector protection/unprotection status (mb84vd2108xem:sa37,sa38 mb84vd2109xem:sa0,sa1) at v ih , allows removal of boot sector protection at v acc , program time will reduse by 40%. ? erase suspend/resume suspends the erase operation to allow a read in another sector within the same device ? please refer to mbm29dl16xte/be datasheet in detailed function * : embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc. sram ? power dissipation operating : 40 ma max standby : 7 m a max ? power down features using ce1 s and ce2s ? data retention supply voltage: 1.5 v to 3.3 v ?ce1 s and ce2s chip select ? byte data control: lb (dq 7 to dq 0 ), ub (dq 15 to dq 8 )
mb84vd2108xem/2109xem -70 3 n pin assignment (bga-56p-m02) (top view) marking side c7 a 13 c6 a 9 c5 n.c. c4 ry/by c3 a 18 c2 a 5 c1 a 2 c8 n.c. e7 sa e6 dq 6 e3 dq 1 e2 v ss e1 a 0 e8 a 16 f7 dq 15 /a -1 f6 dq 13 f5 dq 4 f4 dq 3 f3 dq 9 f2 oe f1 cef f8 ciof d7 a 14 d6 a 10 index land* d3 a 17 d2 a 4 d1 a 1 d8 n.c. g7 dq 7 g6 dq 12 g5 vccs g4 vccf g3 dq 10 g2 dq 0 g1 ce1s g8 vss h7 dq 14 h6 dq 5 h5 cios h4 dq 11 h3 dq 2 h2 dq 8 b7 a 12 b6 a 19 b5 ce2s b4 reset b3 ub b2 a 6 b1 a 3 b8 a 15 a7 a 11 a6 a 8 a5 we a4 wp/acc a3 lb a2 a 7 * : there is no solder ball. this land should be open electrically.
mb84vd2108xem/2109xem -70 4 n pin description pin name function input/output a 16 to a 0 address inputs (common) i a 19 to a 17 , a -1 address input (flash) i sa address input (sram) i dq 15 to dq 0 data inputs / outputs (common) i/o ce f chip enable (flash) i ce1 s chip enable (sram) i ce2s chip enable (sram) i oe output enable (common) i we write enable (common) i ry/by ready/busy outputs (flash) open drain output o ub upper byte control (sram) i lb lower byte control (sram) i ciof i/o configuration (flash) ciof = v cc f is word mode ( 16 ), ciof = v ss is byte mode ( 8 ) i cios i/o configuration (sram) cios = v cc s is word mode ( 16), cios = v ss is byte mode ( 8) i reset hardware reset pin / sector protection un- lock (flash) i wp /acc write protect / acceleration (flash) i n.c. no internal connection v ss device ground (common) power v cc f device power supply (flash) power v cc s device power supply (sram) power
mb84vd2108xem/2109xem -70 5 n block diagram v ss v cc s 16 m bit reset flash memory we 2 m bit static ram ce f a 19 to a 0 oe ce1 s v ss v cc f a 19 to a 0 a 16 to a 0 dq 15 /a C 1 to dq 0 ry/by lb ub ciof wp /acc ce2s dq 15 /a C 1 to dq 0 dq 15 to dq 0 a C1 sa cios
mb84vd2108xem/2109xem -70 6 n device bus operations user bus operations table (flash = word mode; ciof = v cc f, sram = word mode; cios = v cc s) legend: l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. *1 : other operations except for indicated this column are inhibited. *2 : we can be v il if oe is v il , oe at v ih initiates the write operations. *3 : do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. *4 : it is also used for the extended sector group protections. *5 : wp /acc = v il ; protection of boot sectors. wp /acc = v ih ; removal of boot sectors protection. wp /acc = v acc (9 v) ; program time will reduce by 40%. operation * 1, * 3 ce fce1 sce2s oe we sa lb ub dq 7 to dq 0 dq 15 to dq 8 reset wp / acc * 5 full standby h hx xxxxx high-z high-z h x xl output disable hl h h h x x x high-z high-z hx x x x h h high-z high-z l hx h h x x x high-z high-z xl read from flash * 2 l hx lhxxx d out d out hx xl write to flash l hx hlxxx d in d in hx xl read from sram h l h l h x ll d out d out hx hl high-z d out lh d out high-z write to sram h l h x l x ll d in d in hx hl high-z d in lh d in high-z temporary sector group unprotection * 4 xx xxxxxx x x v id x flash hardware reset x hx xxxxx high-z high-z l x xl boot block sector write protection xx xxxxxx x x x l
mb84vd2108xem/2109xem -70 7 user bus operations table (flash = word mode; ciof = v cc f, sram = byte mode; cios = v ss ) legend: l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. *1 : other operations except for indicated this column are inhibited. *2 : we can be v il if oe is v il , oe at v ih initiates the write operations. *3 : do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. *4 : it is also used for the extended sector group protections. *5 : wp /acc = v il ; protection of boot sectors. wp /acc = v ih ; removal of boot sectors protection. wp /acc = v acc (9 v); program time will reduce by 40%. operation * 1, * 3 ce fce1 sce2s oe we sa lb ub dq 7 to dq 0 dq 15 to dq 8 reset wp / acc * 5 full standby h hx xxxxx high-z high-z h x xl output disable hl h h h x x x high-z high-z hx x x x h h high-z high-z l hx h h x x x high-z high-z xl read from flash * 2 l hx lhxxx d out d out hx xl write to flash l hx hlxxx d in d in hx xl read from sram h l h l h sa x x d out high-z h x write to sram h l h x l sa x x d in high-z h x temporary sector group unprotection * 4 xx xxxxxx x x v id x flash hardware reset x hx xxxxx high-z high-z l x xl boot block sector write protection xx xxxxxx x x x l
mb84vd2108xem/2109xem -70 8 user bus operations table (flash = byte mode; ciof = v ss , sram = byte mode; cios = v ss ) legend: l = v il , h = v ih , x = v il or v ih . see dc characteristics for voltage levels. *1 : other operations except for indicated this column are inhibited. *2 : we can be v il if oe is v il , oe at v ih initiates the write operations. *3 : do not apply ce f = v il , ce1 s = v il and ce2s = v ih at a time. *4 : it is also used for the extended sector group protections. *5 : wp /acc = v il ; protection of boot sectors. wp /acc = v ih ; removal of boot sectors protection. wp /acc = v acc (9 v); program time will reduce by 40%. operation * 1, * 3 ce fce1 sce2sdq 15 /a C 1 oe we sa lb ub dq 7 to dq 0 dq 14 to dq 8 reset wp / acc * 5 full standby h hx x x x x x x high-z high-z h x xl output disable hl h x h h x x x high-z high-z hx x x x x h h high-z high-z l hx a C1 h h x x x high-z high-z xl read from flash * 2 l hx a C1 lhx x x d out high-z h x xl write to flash l hx a C1 hlx x x d in high-z h x xl read from sram h l h x l h sa x x d out high-z h x write to sram h l h x x l sa x x d in high-z h x temporary sector group unprotection * 4 x x x x xxx x x x x v id x flash hardware re- set x hx x x x x x x high-z high-z l x xl boot block sector write protection x x x x xxx x x x x x l
mb84vd2108xem/2109xem -70 9 n absolute maximum ratings *1 : minimum dc voltage on input or i/o pins is C0.3 v. during voltage transitions, input or i/o pins may undershoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f+0.4 v or v cc s+0.4 v. during voltage transitions, input or i/o pins may overshoot to v cc f+2.0 v or v cc s+2.0 v for periods of up to 20 ns. *2 : minimum dc input voltage on reset pin is C0.5 v. during voltage transitions, reset pins may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (vin-v cc f or v cc s) does not exceed +9.0 v. maximum dc input voltage on reset pins is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. *3 : minimum dc input voltage on wp /acc pin is C0.5 v. during voltage transitions, wp /acc pin may undershoot vss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +12.0 v for periods of up to 20 ns, when v cc f is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions note: operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg C55 +125 c ambient temperature with power applied t a C40 +85 c voltage with respect to ground all pins except reset , wp /acc * 1 v in , v out C0.3 v cc f +0.4 v v cc s +0.4 v v cc f/v cc s supply * 1 v cc f, v cc s C0.3 +4.0 v reset * 2 v in C0.5 + 13.0 v wp /acc * 3 v in C0.5 +10.5 v parameter symbol value unit min max ambient temperature t a C40 +85 c v cc f/v cc s supply voltages vccf, vccs +2.7 +3.3 v
mb84vd2108xem/2109xem -70 10 n electrical characteristics 1. dc characteristics (continued) parameter symbol test conditions value unit min typ max input leakage current i li v in = v ss to v cc f, v cc s C1.0 +1.0 m a output leakage current i lo v out = v ss to v cc f, v cc s C1.0 +1.0 m a reset inputs leakage current i lit v cc f = v cc f max, v cc s = v cc s max, reset = 12.5 v 35 a flash v cc active current (read) * 1 i cc1 f ce f = v il , oe = v ih t cycle = 5 mhz byte 13 ma t cycle = 5 mhz word 15 t cycle = 1 mhz byte 7 ma t cycle = 1 mhz word 7 flash v cc active current (program/erase) * 2 i cc2 f ce f = v il , oe = v ih 35ma flash v cc active current (read-while-program) * 5 i cc3 fce f = v il , oe = v ih byte 48 ma word 50 flash v cc active current (read-while-erase) * 5 i cc4 fce f = v il , oe = v ih byte 48 ma word 50 flash v cc active current (erase-suspend-program) i cc5 fce f = v il , oe = v ih 35ma acc input leakage current i lia v cc f = v cc f max, v cc s = v cc s max, wp /acc = v acc max 20ma sram v cc active current i cc1 s v cc s = v cc s max, ce1 s = v il , ce2s = v ih t cycle =10 mhz 40 ma sram v cc active current i cc2 s ce1 s = 0.2 v, ce2s = v cc s C 0.2 v t cycle = 10 mhz 40 ma t cycle = 1 mhz 8 ma flash v cc standby current i sb1 f v cc f = v cc f max, ce f = v cc f 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v 15 m a flash v cc standby current (reset ) i sb2 f v cc f = v cc f max, reset = v ss 0.3 v, wp /acc = v cc f 0.3 v 15 m a flash v cc current (automatic sleep mode) * 3 i sb3 f v cc f = v cc f max, ce f = v ss 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v v in = v cc f 0.3 v or v ss 0.3 v 15 m a
mb84vd2108xem/2109xem -70 11 (continued) * 1 : the i cc current listed includes both the dc operating current and the frequency dependent component. *2 : i cc active while embedded algorithm (program or erase) is in progress. *3 : automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4 : applicable for only v cc f applying. *5 : embedded algorithm (program or erase) is in progress. (@5 mhz) *6 : v cc indicates lower of v cc f or v cc s. parameter symbol test conditions value unit min typ max sram v cc standby current i sb1 s ce1 s > v cc s C 0.2 v, ce2s > v cc s C 0.2 v lb = ub > v cc sC0.2 v or < 0.2 v 7 m a sram v cc standby current i sb2 s ce1 s > v cc s C 0.2 v or < 0.2 v, ce2s < 0.2 v lb = ub > v cc sC0.2 v or < 0.2v 7 m a input low level v il C0.3 0.5 v input high level v ih 2.4 v cc +0.3 * 6 v voltage for sector protection, and temporary sector unprotection (reset ) * 4 v id 11.5 12.5 v voltage for program acceleration (wp /acc) * 4 v acc 8.59.09.5v sram output low level v ol v cc s = v cc s min, i ol = 4.0 ma 0.45 v sram output high level v oh v cc s = v cc s min, i oh = C0.5 ma 2.4 v flash output low level v ol v cc f = v cc f min, i ol = 4.0 ma 0.4 v flash output high level v oh v cc f = v cc f min, i oh = C0.5 ma 2.4 v flash low v cc f lock-out voltage v lko 2.32.5v
mb84vd2108xem/2109xem -70 12 2. ac characteristics ? ce timing ? timing diagram for alternating sram to flash ? flash characteristics please refer to n 16m flash memory characteristics for mcp part. ? sram characteristics, please refer to n 2m sram characteristics for mcp part. parameter symbol test setup value unit jedec standard min ce recover time t ccr 0ns ce f t ccr t ccr ce1 s ce2s t ccr t ccr
mb84vd2108xem/2109xem -70 13 n 16m flash memory characteristics for mcp 1. flexible sector-erase architecture on flash memory ? eight 4 k words, and thirty one 32 k words. ? individual-sector, multiple-sector, or bulk-erase capability. bank 1 bank size 1 bank 2 bank 1 bank size 2 bank 1 bank 1 bank 2 bank 2 bank 2 sector architecture (top boot block) 010000h sa0 : 64kb (32kw) 000000h 030000h 020000h 050000h 040000h 070000h 060000h 090000h 080000h 0b0000h 0a0000h 0d0000h 0c0000h 0f0000h 0e0000h sa1 : 64kb (32kw) sa2 : 64kb (32kw) sa3 : 64kb (32kw) sa4 : 64kb (32kw) sa5 : 64kb (32kw) sa6 : 64kb (32kw) sa7 : 64kb (32kw) sa8 : 64kb (32kw) sa9 : 64kb (32kw) sa10 : 64kb (32kw) sa11 : 64kb (32kw) sa12 : 64kb (32kw) sa13 : 64kb (32kw) sa14 : 64kb (32kw) sa15 : 64kb (32kw) sa16 : 64kb (32kw) sa17 : 64kb (32kw) sa18 : 64kb (32kw) sa19 : 64kb (32kw) sa20 : 64kb (32kw) sa21 : 64kb (32kw) sa22 : 64kb (32kw) sa23 : 64kb (32kw) sa24 : 64kb (32kw) sa25 : 64kb (32kw) sa26 : 64kb (32kw) sa27 : 64kb (32kw) sa28 : 64kb (32kw) sa29 : 64kb (32kw) sa30 : 64kb (32kw) sa31 : 8kb (4kw) sa32 : 8kb (4kw) sa33 : 8kb (4kw) sa34 : 8kb (4kw) sa35 : 8kb (4kw) sa36 : 8kb (4kw) sa37 : 8kb (4kw) sa38 : 8kb (4kw) 110000h 100000h 130000h 120000h 150000h 140000h 170000h 160000h 190000h 180000h 1b0000h 1a0000h 1d0000h 1c0000h 1f0000h 1e0000h 1f2000h 1f6000h 1f4000h 1fa000h 1f8000h 1fe000h 1fc000h 1fffffh 008000h 000000h 018000h 010000h 028000h 020000h 038000h 030000h 048000h 040000h 058000h 050000h 068000h 060000h 078000h 070000h 088000h 080000h 098000h 090000h 0a8000h 0a0000h 0b8000h 0b0000h 0c8000h 0c0000h 0d8000h 0d0000h 0e8000h 0e0000h 0f8000h 0f0000h 0f9000h 0fb000h 0fa000h 0fd000h 0fc000h 0ff000h 0fe000h 0fffffh word mode byte mode bank size 3 bank size 4
mb84vd2108xem/2109xem -70 14 (continued) (continued) sector architecture (bottom boot block) bank 2 bank 1 bank 2 bank 2 bank 2 bank 1 bank 1 bank 1 010000h word mode byte mode sa0 : 8kb (4kw) 000000h 030000h 020000h 050000h 040000h 070000h 060000h 090000h 080000h 0b0000h 0a0000h 0d0000h 0c0000h 0f0000h 0e0000h sa1 : 8kb (4kw) sa2 : 8kb (4kw) sa3 : 8kb (4kw) sa4 : 8kb (4kw) sa5 : 8kb (4kw) sa6 : 8kb (4kw) sa7 : 8kb (4kw) sa8 : 64kb (32kw) sa9 : 64kb (32kw) sa10 : 64kb (32kw) sa11 : 64kb (32kw) sa12 : 64kb (32kw) sa13 : 64kb (32kw) sa14 : 64kb (32kw) sa15 : 64kb (32kw) sa16 : 64kb (32kw) sa17 : 64kb (32kw) sa18 : 64kb (32kw) sa19 : 64kb (32kw) sa20 : 64kb (32kw) sa21 : 64kb (32kw) sa22 : 64kb (32kw) sa23 : 64kb (32kw) sa24 : 64kb (32kw) sa25 : 64kb (32kw) sa26 : 64kb (32kw) sa27 : 64kb (32kw) sa28 : 64kb (32kw) sa29 : 64kb (32kw) sa30 : 64kb (32kw) sa31 : 64kb (32kw) sa32 : 64kb (32kw) sa33 : 64kb (32kw) sa34 : 64kb (32kw) sa35 : 64kb (32kw) sa36 : 64kb (32kw) sa37 : 64kb (32kw) sa38 : 64kb (32kw) 110000h 100000h 130000h 120000h 150000h 140000h 170000h 160000h 190000h 180000h 1b0000h 1a0000h 1d0000h 1c0000h 1f0000h 1e0000h 1fffffh 008000h 000000h 018000h 010000h 028000h 020000h 038000h 030000h 048000h 040000h 058000h 050000h 068000h 060000h 078000h 070000h 088000h 080000h 098000h 090000h 0a8000h 0a0000h 0b8000h 0b0000h 0c8000h 0c0000h 0d8000h 0d0000h 0e8000h 0e0000h 0f8000h 0f0000h 0fffffh 002000h 006000h 004000h 00a000h 008000h 00e000h 00c000h 001000h 003000h 002000h 005000h 004000h 007000h 006000h bank size 1 bank size 2 bank size 3 bank size 4
mb84vd2108xem/2109xem -70 15 sector address table (top boot block, bank size=1) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 0 0 0 0 0 x x x 000000h to 00ffffh 000000h to 007fffh sa1 0 0 0 0 1 x x x 010000h to 01ffffh 008000h to 00ffffh sa2 0 0 0 1 0 x x x 020000h to 02ffffh 010000h to 017fffh sa3 0 0 0 1 1 x x x 030000h to 03ffffh 018000h to 01ffffh sa4 0 0 1 0 0 x x x 040000h to 04ffffh 020000h to 027fffh sa5 0 0 1 0 1 x x x 050000h to 05ffffh 028000h to 02ffffh sa6 0 0 1 1 0 x x x 060000h to 06ffffh 030000h to 037fffh sa7 0 0 1 1 1 x x x 070000h to 07ffffh 038000h to 03ffffh sa8 0 1 0 0 0 x x x 080000h to 08ffffh 040000h to 047fffh sa9 0 1 0 0 1 x x x 090000h to 09ffffh 048000h to 04ffffh sa10 0 1 0 1 0 x x x 0a0000h to 0affffh 050000h to 057fffh sa11 0 1 0 1 1 x x x 0b0000h to 0bffffh 058000h to 05ffffh sa12 0 1 1 0 0 x x x 0c0000h to 0cffffh 060000h to 067fffh sa13 0 1 1 0 1 x x x 0d0000h to 0dffffh 068000h to 06ffffh sa14 0 1 1 1 0 x x x 0e0000h to 0effffh 070000h to 077fffh sa15 0 1 1 1 1 x x x 0f0000h to 0fffffh 078000h to 07ffffh sa16 1 0 0 0 0 x x x 100000h to 10ffffh 080000h to 087fffh sa17 1 0 0 0 1 x x x 110000h to 11ffffh 088000h to 08ffffh sa18 1 0 0 1 0 x x x 120000h to 12ffffh 090000h to 097fffh sa19 1 0 0 1 1 x x x 130000h to 13ffffh 098000h to 09ffffh sa20 1 0 1 0 0 x x x 140000h to 14ffffh 0a0000h to 0a7fffh sa21 1 0 1 0 1 x x x 150000h to 15ffffh 0a8000h to 0affffh sa22 1 0 1 1 0 x x x 160000h to 16ffffh 0b0000h to 0b7fffh sa23 1 0 1 1 1 x x x 170000h to 17ffffh 0b8000h to 0bffffh sa24 1 1 0 0 0 x x x 180000h to 18ffffh 0c0000h to 0c7fffh sa25 1 1 0 0 1 x x x 190000h to 19ffffh 0c8000h to 0cffffh sa26 1 1 0 1 0 x x x 1a0000h to 1affffh 0d0000h to 0d7fffh sa27 1 1 0 1 1 x x x 1b0000h to 1bffffh 0d8000h to 0dffffh sa28 1 1 1 0 0 x x x 1c0000h to 1cffffh 0e0000h to 0e7fffh sa29 1 1 1 0 1 x x x 1d0000h to 1dffffh 0e8000h to 0effffh sa30 1 1 1 1 0 x x x 1e0000h to 1effffh 0f0000h to 0f7fffh bank 1 sa31 1 1 1 1 1 0 0 0 1f0000h to 1f1fffh 0f8000h to 0f8fffh sa32 1 1 1 1 1 0 0 1 1f2000h to 1f3fffh 0f9000h to 0f9fffh sa33 1 1 1 1 1 0 1 0 1f4000h to 1f5fffh 0fa000h to 0fafffh sa34 1 1 1 1 1 0 1 1 1f6000h to 1f7fffh 0fb000h to 0fbfffh sa35 1 1 1 1 1 1 0 0 1f8000h to 1f9fffh 0fc000h to 0fcfffh sa36 1 1 1 1 1 1 0 1 1fa000h to 1fbfffh 0fd000h to 0fdfffh sa37 1 1 1 1 1 1 1 0 1fc000h to 1fdfffh 0fe000h to 0fefffh sa38 1 1 1 1 1 1 1 1 1fe000h to 1fffffh 0ff000h to 0fffffh
mb84vd2108xem/2109xem -70 16 sector address table (bottom boot block, bank size=1) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 1 sa0 00000000000000h to 001 fffh 000000h to 000fffh sa1 00000001002000h to 003 fffh 001000h to 001fffh sa2 00000010004000h to 005 fffh 002000h to 002fffh sa3 00000011006000h to 007 fffh 003000h to 003fffh sa4 00000100008000h to 009 fffh 004000h to 004fffh sa5 0000010100a000h to 00b fffh 005000h to 005fffh sa6 0000011000c000h to 00d fffh 006000h to 006fffh sa7 0000011100e000h to 00 ffffh 007000h to 007fffh bank 2 sa8 0 0 0 0 1 x x x 010000h to 01ffffh 008000h to 00ffffh sa9 0 0 0 1 0 x x x 020000h to 02ffffh 010000h to 017fffh sa10 0 0 0 1 1 x x x 030000h to 03ffffh 018000h to 01ffffh sa11 0 0 1 0 0 x x x 040000h to 04ffffh 020000h to 027fffh sa12 0 0 1 0 1 x x x 050000h to 05ffffh 028000h to 02ffffh sa13 0 0 1 1 0 x x x 060000h to 06ffffh 030000h to 037fffh sa14 0 0 1 1 1 x x x 070000h to 07ffffh 038000h to 03ffffh sa15 0 1 0 0 0 x x x 080000h to 08ffffh 040000h to 047fffh sa16 0 1 0 0 1 x x x 090000h to 09ffffh 048000h to 04ffffh sa17 0 1 0 1 0 x x x 0a0000h to 0affffh 050000h to 057fffh sa18 0 1 0 1 1 x x x 0b0000h to 0bffffh 058000h to 05ffffh sa19 0 1 1 0 0 x x x 0c0000h to 0cffffh 060000h to 067fffh sa20 0 1 1 0 1 x x x 0d0000h to 0dffffh 068000h to 06ffffh sa21 0 1 1 1 0 x x x 0e0000h to 0effffh 070000h to 077fffh sa22 0 1 1 1 1 x x x 0f0000h to 0fffffh 078000h to 07ffffh sa23 1 0 0 0 0 x x x 100000h to 10ffffh 080000h to 087fffh sa24 1 0 0 0 1 x x x 110000h to 11ffffh 088000h to 08ffffh sa25 1 0 0 1 0 x x x 120000h to 12ffffh 090000h to 097fffh sa26 1 0 0 1 1 x x x 130000h to 13ffffh 098000h to 09ffffh sa27 1 0 1 0 0 x x x 140000h to 14ffffh 0a0000h to 0a7fffh sa28 1 0 1 0 1 x x x 150000h to 15ffffh 0a8000h to 0affffh sa29 1 0 1 1 0 x x x 160000h to 16ffffh 0b0000h to 0b7fffh sa30 1 0 1 1 1 x x x 170000h to 17ffffh 0b8000h to 0bffffh sa31 1 1 0 0 0 x x x 180000h to 18ffffh 0c0000h to 0c7fffh sa32 1 1 0 0 1 x x x 190000h to 19ffffh 0c8000h to 0cffffh sa33 1 1 0 1 0 x x x 1a0000h to 1affffh 0d0000h to 0d7fffh sa34 1 1 0 1 1 x x x 1b0000h to 1bffffh 0d8000h to 0dffffh sa35 1 1 1 0 0 x x x 1c0000h to 1cffffh 0e0000h to 0e7fffh sa36 1 1 1 0 1 x x x 1d0000h to 1dffffh 0e8000h to 0effffh sa37 1 1 1 1 0 x x x 1e0000h to 1effffh 0f0000h to 0f7fffh sa38 1 1 1 1 1 x x x 1f0000h to 1fffffh 0f8000h to 0fffffh
mb84vd2108xem/2109xem -70 17 sector address table (top boot block, bank size=2) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 0 0 0 0 0 x x x 000000h to 00ffffh 000000h to 007fffh sa1 0 0 0 0 1 x x x 010000h to 01ffffh 008000h to 00ffffh sa2 0 0 0 1 0 x x x 020000h to 02ffffh 010000h to 017fffh sa3 0 0 0 1 1 x x x 030000h to 03ffffh 018000h to 01ffffh sa4 0 0 1 0 0 x x x 040000h to 04ffffh 020000h to 027fffh sa5 0 0 1 0 1 x x x 050000h to 05ffffh 028000h to 02ffffh sa6 0 0 1 1 0 x x x 060000h to 06ffffh 030000h to 037fffh sa7 0 0 1 1 1 x x x 070000h to 07ffffh 038000h to 03ffffh sa8 0 1 0 0 0 x x x 080000h to 08ffffh 040000h to 047fffh sa9 0 1 0 0 1 x x x 090000h to 09ffffh 048000h to 04ffffh sa10 0 1 0 1 0 x x x 0a0000h to 0affffh 050000h to 057fffh sa11 0 1 0 1 1 x x x 0b0000h to 0bffffh 058000h to 05ffffh sa12 0 1 1 0 0 x x x 0c0000h to 0cffffh 060000h to 067fffh sa13 0 1 1 0 1 x x x 0d0000h to 0dffffh 068000h to 06ffffh sa14 0 1 1 1 0 x x x 0e0000h to 0effffh 070000h to 077fffh sa15 0 1 1 1 1 x x x 0f0000h to 0fffffh 078000h to 07ffffh sa16 1 0 0 0 0 x x x 100000h to 10ffffh 080000h to 087fffh sa17 1 0 0 0 1 x x x 110000h to 11ffffh 088000h to 08ffffh sa18 1 0 0 1 0 x x x 120000h to 12ffffh 090000h to 097fffh sa19 1 0 0 1 1 x x x 130000h to 13ffffh 098000h to 09ffffh sa20 1 0 1 0 0 x x x 140000h to 14ffffh 0a0000h to 0a7fffh sa21 1 0 1 0 1 x x x 150000h to 15ffffh 0a8000h to 0affffh sa22 1 0 1 1 0 x x x 160000h to 16ffffh 0b0000h to 0b7fffh sa23 1 0 1 1 1 x x x 170000h to 17ffffh 0b8000h to 0bffffh sa24 1 1 0 0 0 x x x 180000h to 18ffffh 0c0000h to 0c7fffh sa25 1 1 0 0 1 x x x 190000h to 19ffffh 0c8000h to 0cffffh sa26 1 1 0 1 0 x x x 1a0000h to 1affffh 0d0000h to 0d7fffh sa27 1 1 0 1 1 x x x 1b0000h to 1bffffh 0d8000h to 0dffffh bank 1 sa28 1 1 1 0 0 x x x 1c0000h to 1cffffh 0e0000h to 0e7fffh sa29 1 1 1 0 1 x x x 1d0000h to 1dffffh 0e8000h to 0effffh sa30 1 1 1 1 0 x x x 1e0000h to 1effffh 0f0000h to 0f7fffh sa31111110001f0000h to 1f1 fffh 0f8000h to 0f8fffh sa32111110011f2000h to 1f3 fffh 0f9000h to 0f9fffh sa33111110101f4000h to 1f5 fffh 0fa000h to 0fafffh sa34111110111f6000h to 1f7 fffh 0fb000h to 0fbfffh sa35111111001f8000h to 1f9 fffh 0fc000h to 0fcfffh sa36111111011fa000h to 1fb fffh 0fd000h to 0fdfffh sa37111111101fc000h to 1fd fffh 0fe000h to 0fefffh sa38111111111fe000h to 1 fffffh 0ff000h to 0fffffh
mb84vd2108xem/2109xem -70 18 sector address table (bottom boot block, bank size=2) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 1 sa0 0 0 0 0 0 0 0 0 000000h to 001fffh 000000h to 000fffh sa1 0 0 0 0 0 0 0 1 002000h to 003fffh 001000h to 001fffh sa2 0 0 0 0 0 0 1 0 004000h to 005fffh 002000h to 002fffh sa3 0 0 0 0 0 0 1 1 006000h to 007fffh 003000h to 003fffh sa4 0 0 0 0 0 1 0 0 008000h to 009fffh 004000h to 004fffh sa5 0 0 0 0 0 1 0 1 00a000h to 00bfffh 005000h to 005fffh sa6 0 0 0 0 0 1 1 0 00c000h to 00dfffh 006000h to 006fffh sa7 0 0 0 0 0 1 1 1 00e000h to 00ffffh 007000h to 007fffh sa8 0 0 0 0 1 x x x 010000h to 01ffffh 008000h to 00ffffh sa9 0 0 0 1 0 x x x 020000h to 02ffffh 010000h to 017fffh sa10 0 0 0 1 1 x x x 030000h to 03ffffh 018000h to 01ffffh bank 2 sa11 0 0 1 0 0 x x x 040000h to 04ffffh 020000h to 027fffh sa12 0 0 1 0 1 x x x 050000h to 05ffffh 028000h to 02ffffh sa13 0 0 1 1 0 x x x 060000h to 06ffffh 030000h to 037fffh sa14 0 0 1 1 1 x x x 070000h to 07ffffh 038000h to 03ffffh sa15 0 1 0 0 0 x x x 080000h to 08ffffh 040000h to 047fffh sa16 0 1 0 0 1 x x x 090000h to 09ffffh 048000h to 04ffffh sa17 0 1 0 1 0 x x x 0a0000h to 0affffh 050000h to 057fffh sa18 0 1 0 1 1 x x x 0b0000h to 0bffffh 058000h to 05ffffh sa19 0 1 1 0 0 x x x 0c0000h to 0cffffh 060000h to 067fffh sa20 0 1 1 0 1 x x x 0d0000h to 0dffffh 068000h to 06ffffh sa21 0 1 1 1 0 x x x 0e0000h to 0effffh 070000h to 077fffh sa22 0 1 1 1 1 x x x 0f0000h to 0fffffh 078000h to 07ffffh sa23 1 0 0 0 0 x x x 100000h to 10ffffh 080000h to 087fffh sa24 1 0 0 0 1 x x x 110000h to 11ffffh 088000h to 08ffffh sa25 1 0 0 1 0 x x x 120000h to 12ffffh 090000h to 097fffh sa26 1 0 0 1 1 x x x 130000h to 13ffffh 098000h to 09ffffh sa27 1 0 1 0 0 x x x 140000h to 14ffffh 0a0000h to 0a7fffh sa28 1 0 1 0 1 x x x 150000h to 15ffffh 0a8000h to 0affffh sa29 1 0 1 1 0 x x x 160000h to 16ffffh 0b0000h to 0b7fffh sa30 1 0 1 1 1 x x x 170000h to 17ffffh 0b8000h to 0bffffh sa31 1 1 0 0 0 x x x 180000h to 18ffffh 0c0000h to 0c7fffh sa32 1 1 0 0 1 x x x 190000h to 19ffffh 0c8000h to 0cffffh sa33 1 1 0 1 0 x x x 1a0000h to 1affffh 0d0000h to 0d7fffh sa34 1 1 0 1 1 x x x 1b0000h to 1bffffh 0d8000h to 0dffffh sa35 1 1 1 0 0 x x x 1c0000h to 1cffffh 0e0000h to 0e7fffh sa36 1 1 1 0 1 x x x 1d0000h to 1dffffh 0e8000h to 0effffh sa37 1 1 1 1 0 x x x 1e0000h to 1effffh 0f0000h to 0f7fffh sa38 1 1 1 1 1 x x x 1f0000h to 1fffffh 0f8000h to 0fffffh
mb84vd2108xem/2109xem -70 19 sector address table (top boot block, bank size=3) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 0 0 0 0 0 x x x 000000h to 00ffffh 000000h to 007fffh sa1 0 0 0 0 1 x x x 010000h to 01ffffh 008000h to 00ffffh sa2 0 0 0 1 0 x x x 020000h to 02ffffh 010000h to 017fffh sa3 0 0 0 1 1 x x x 030000h to 03ffffh 018000h to 01ffffh sa4 0 0 1 0 0 x x x 040000h to 04ffffh 020000h to 027fffh sa5 0 0 1 0 1 x x x 050000h to 05ffffh 028000h to 02ffffh sa6 0 0 1 1 0 x x x 060000h to 06ffffh 030000h to 037fffh sa7 0 0 1 1 1 x x x 070000h to 07ffffh 038000h to 03ffffh sa8 0 1 0 0 0 x x x 080000h to 08ffffh 040000h to 047fffh sa9 0 1 0 0 1 x x x 090000h to 09ffffh 048000h to 04ffffh sa10 0 1 0 1 0 x x x 0a0000h to 0affffh 050000h to 057fffh sa11 0 1 0 1 1 x x x 0b0000h to 0bffffh 058000h to 05ffffh sa12 0 1 1 0 0 x x x 0c0000h to 0cffffh 060000h to 067fffh sa13 0 1 1 0 1 x x x 0d0000h to 0dffffh 068000h to 06ffffh sa14 0 1 1 1 0 x x x 0e0000h to 0effffh 070000h to 077fffh sa15 0 1 1 1 1 x x x 0f0000h to 0fffffh 078000h to 07ffffh sa16 1 0 0 0 0 x x x 100000h to 10ffffh 080000h to 087fffh sa17 1 0 0 0 1 x x x 110000h to 11ffffh 088000h to 08ffffh sa18 1 0 0 1 0 x x x 120000h to 12ffffh 090000h to 097fffh sa19 1 0 0 1 1 x x x 130000h to 13ffffh 098000h to 09ffffh sa20 1 0 1 0 0 x x x 140000h to 14ffffh 0a0000h to 0a7fffh sa21 1 0 1 0 1 x x x 150000h to 15ffffh 0a8000h to 0affffh sa22 1 0 1 1 0 x x x 160000h to 16ffffh 0b0000h to 0b7fffh sa23 1 0 1 1 1 x x x 170000h to 17ffffh 0b8000h to 0bffffh bank 1 sa24 1 1 0 0 0 x x x 180000h to 18ffffh 0c0000h to 0c7fffh sa25 1 1 0 0 1 x x x 190000h to 19ffffh 0c8000h to 0cffffh sa26 1 1 0 1 0 x x x 1a0000h to 1affffh 0d0000h to 0d7fffh sa27 1 1 0 1 1 x x x 1b0000h to 1bffffh 0d8000h to 0dffffh sa28 1 1 1 0 0 x x x 1c0000h to 1cffffh 0e0000h to 0e7fffh sa29 1 1 1 0 1 x x x 1d0000h to 1dffffh 0e8000h to 0effffh sa30 1 1 1 1 0 x x x 1e0000h to 1effffh 0f0000h to 0f7fffh sa31111110001f0000h to 1f1 fffh 0f8000h to 0f8fffh sa32111110011f2000h to 1f3 fffh 0f9000h to 0f9fffh sa33111110101f4000h to 1f5 fffh 0fa000h to 0fafffh sa34111110111f6000h to 1f7 fffh 0fb000h to 0fbfffh sa35111111001f8000h to 1f9 fffh 0fc000h to 0fcfffh sa36111111011fa000h to 1fb fffh 0fd000h to 0fdfffh sa37111111101fc000h to 1fd fffh 0fe000h to 0fefffh sa38111111111fe000h to 1 fffffh 0ff000h to 0fffffh
mb84vd2108xem/2109xem -70 20 sector address table (bottom boot block, bank size=3) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 1 sa0 00000000000000h to 001 fffh 000000h to 000fffh sa1 00000001002000h to 003 fffh 001000h to 001fffh sa2 00000010004000h to 005 fffh 002000h to 002fffh sa3 00000011006000h to 007 fffh 003000h to 003fffh sa4 00000100008000h to 009 fffh 004000h to 004fffh sa5 0000010100a000h to 00b fffh 005000h to 005fffh sa6 0000011000c000h to 00d fffh 006000h to 006fffh sa7 0000011100e000h to 00 ffffh 007000h to 007fffh sa8 00001xxx010000h to 01 ffffh 008000h to 00ffffh sa9 00010xxx020000h to 02 ffffh 010000h to 017fffh sa1000011xxx030000h to 03 ffffh 018000h to 01ffffh sa1100100xxx040000h to 04 ffffh 020000h to 027fffh sa1200101xxx050000h to 05 ffffh 028000h to 02ffffh sa1300110xxx060000h to 06 ffffh 030000h to 037fffh sa1400111xxx070000h to 07 ffffh 038000h to 03ffffh bank 2 sa1501000xxx080000h to 08 ffffh 040000h to 047fffh sa1601001xxx090000h to 09 ffffh 048000h to 04ffffh sa1701010xxx0a0000h to 0a ffffh 050000h to 057fffh sa1801011xxx0b0000h to 0b ffffh 058000h to 05ffffh sa1901100xxx0c0000h to 0c ffffh 060000h to 067fffh sa2001101xxx0d0000h to 0d ffffh 068000h to 06ffffh sa2101110xxx0e0000h to 0e ffffh 070000h to 077fffh sa2201111xxx0f0000h to 0ff fffh 078000h to 07ffffh sa2310000xxx100000h to 10 ffffh 080000h to 087fffh sa2410001xxx110000h to 11 ffffh 088000h to 08ffffh sa2510010xxx120000h to 12 ffffh 090000h to 097fffh sa2610011xxx130000h to 13 ffffh 098000h to 09ffffh sa2710100xxx140000h to 14 ffffh 0a0000h to 0a7fffh sa2810101xxx150000h to 15 ffffh 0a8000h to 0affffh sa2910110xxx160000h to 16 ffffh 0b0000h to 0b7fffh sa3010111xxx170000h to 17 ffffh 0b8000h to 0bffffh sa3111000xxx180000h to 18 ffffh 0c0000h to 0c7fffh sa3211001xxx190000h to 19 ffffh 0c8000h to 0cffffh sa3311010xxx1a0000h to 1a ffffh 0d0000h to 0d7fffh sa3411011xxx1b0000h to 1b ffffh 0d8000h to 0dffffh sa3511100xxx1c0000h to 1c ffffh 0e0000h to 0e7fffh sa3611101xxx1d0000h to 1d ffffh 0e8000h to 0effffh sa3711110xxx1e0000h to 1e ffffh 0f0000h to 0f7fffh sa3811111xxx1f0000h to 1ff fffh 0f8000h to 0fffffh
mb84vd2108xem/2109xem -70 21 sector address table (top boot block, bank size=4) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 0 0 0 0 0 x x x 000000h to 00ffffh 000000h to 007fffh sa1 0 0 0 0 1 x x x 010000h to 01ffffh 008000h to 00ffffh sa2 0 0 0 1 0 x x x 020000h to 02ffffh 010000h to 017fffh sa3 0 0 0 1 1 x x x 030000h to 03ffffh 018000h to 01ffffh sa4 0 0 1 0 0 x x x 040000h to 04ffffh 020000h to 027fffh sa5 0 0 1 0 1 x x x 050000h to 05ffffh 028000h to 02ffffh sa6 0 0 1 1 0 x x x 060000h to 06ffffh 030000h to 037fffh sa7 0 0 1 1 1 x x x 070000h to 07ffffh 038000h to 03ffffh sa8 0 1 0 0 0 x x x 080000h to 08ffffh 040000h to 047fffh sa9 0 1 0 0 1 x x x 090000h to 09ffffh 048000h to 04ffffh sa10 0 1 0 1 0 x x x 0a0000h to 0affffh 050000h to 057fffh sa11 0 1 0 1 1 x x x 0b0000h to 0bffffh 058000h to 05ffffh sa12 0 1 1 0 0 x x x 0c0000h to 0cffffh 060000h to 067fffh sa13 0 1 1 0 1 x x x 0d0000h to 0dffffh 068000h to 06ffffh sa14 0 1 1 1 0 x x x 0e0000h to 0effffh 070000h to 077fffh sa15 0 1 1 1 1 x x x 0f0000h to 0fffffh 078000h to 07ffffh bank 1 sa16 1 0 0 0 0 x x x 100000h to 10ffffh 080000h to 087fffh sa17 1 0 0 0 1 x x x 110000h to 11ffffh 088000h to 08ffffh sa18 1 0 0 1 0 x x x 120000h to 12ffffh 090000h to 097fffh sa19 1 0 0 1 1 x x x 130000h to 13ffffh 098000h to 09ffffh sa20 1 0 1 0 0 x x x 140000h to 14ffffh 0a0000h to 0a7fffh sa21 1 0 1 0 1 x x x 150000h to 15ffffh 0a8000h to 0affffh sa22 1 0 1 1 0 x x x 160000h to 16ffffh 0b0000h to 0b7fffh sa23 1 0 1 1 1 x x x 170000h to 17ffffh 0b8000h to 0bffffh sa24 1 1 0 0 0 x x x 180000h to 18ffffh 0c0000h to 0c7fffh sa25 1 1 0 0 1 x x x 190000h to 19ffffh 0c8000h to 0cffffh sa26 1 1 0 1 0 x x x 1a0000h to 1affffh 0d0000h to 0d7fffh sa27 1 1 0 1 1 x x x 1b0000h to 1bffffh 0d8000h to 0dffffh sa28 1 1 1 0 0 x x x 1c0000h to 1cffffh 0e0000h to 0e7fffh sa29 1 1 1 0 1 x x x 1d0000h to 1dffffh 0e8000h to 0effffh sa30 1 1 1 1 0 x x x 1e0000h to 1effffh 0f0000h to 0f7fffh sa31111110001f0000h to 1f1 fffh 0f8000h to 0f8fffh sa32111110011f2000h to 1f3 fffh 0f9000h to 0f9fffh sa33111110101f4000h to 1f5 fffh 0fa000h to 0fafffh sa34111110111f6000h to 1f7 fffh 0fb000h to 0fbfffh sa35111111001f8000h to 1f9 fffh 0fc000h to 0fcfffh sa36111111011fa000h to 1fb fffh 0fd000h to 0fdfffh sa37111111101fc000h to 1fdfffh0fe000h to 0fe fffh sa38111111111fe000h to 1fffffh0ff000h to 0 fffffh
mb84vd2108xem/2109xem -70 22 sector address table (bottom boot block, bank size=4) bank sector sector address address range (byte mode) address range (word mode) bank address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 1 sa0 00000000000000h to 001 fffh 000000h to 000fffh sa1 00000001002000h to 003 fffh 001000h to 001fffh sa2 00000010004000h to 005 fffh 002000h to 002fffh sa3 00000011006000h to 007 fffh 003000h to 003fffh sa4 00000100008000h to 009 fffh 004000h to 004fffh sa5 0000010100a000h to 00bfffh005000h to 005 fffh sa6 0000011000c000h to 00d fffh 006000h to 006fffh sa7 0000011100e000h to 00 ffffh 007000h to 007fffh sa8 0 0 0 0 1 x x x 010000h to 01ffffh 008000h to 00ffffh sa9 0 0 0 1 0 x x x 020000h to 02ffffh 010000h to 017fffh sa10 0 0 0 1 1 x x x 030000h to 03ffffh 018000h to 01ffffh sa11 0 0 1 0 0 x x x 040000h to 04ffffh 020000h to 027fffh sa12 0 0 1 0 1 x x x 050000h to 05ffffh 028000h to 02ffffh sa13 0 0 1 1 0 x x x 060000h to 06ffffh 030000h to 037fffh sa14 0 0 1 1 1 x x x 070000h to 07ffffh 038000h to 03ffffh sa15 0 1 0 0 0 x x x 080000h to 08ffffh 040000h to 047fffh sa16 0 1 0 0 1 x x x 090000h to 09ffffh 048000h to 04ffffh sa17 0 1 0 1 0 x x x 0a0000h to 0affffh 050000h to 057fffh sa18 0 1 0 1 1 x x x 0b0000h to 0bffffh 058000h to 05ffffh sa19 0 1 1 0 0 x x x 0c0000h to 0cffffh 060000h to 067fffh sa20 0 1 1 0 1 x x x 0d0000h to 0dffffh 068000h to 06ffffh sa21 0 1 1 1 0 x x x 0e0000h to 0effffh 070000h to 077fffh sa22 0 1 1 1 1 x x x 0f0000h to 0fffffh 078000h to 07ffffh bank 2 sa23 1 0 0 0 0 x x x 100000h to 10ffffh 080000h to 087fffh sa24 1 0 0 0 1 x x x 110000h to 11ffffh 088000h to 08ffffh sa25 1 0 0 1 0 x x x 120000h to 12ffffh 090000h to 097fffh sa26 1 0 0 1 1 x x x 130000h to 13ffffh 098000h to 09ffffh sa27 1 0 1 0 0 x x x 140000h to 14ffffh 0a0000h to 0a7fffh sa28 1 0 1 0 1 x x x 150000h to 15ffffh 0a8000h to 0affffh sa29 1 0 1 1 0 x x x 160000h to 16ffffh 0b0000h to 0b7fffh sa30 1 0 1 1 1 x x x 170000h to 17ffffh 0b8000h to 0bffffh sa31 1 1 0 0 0 x x x 180000h to 18ffffh 0c0000h to 0c7fffh sa32 1 1 0 0 1 x x x 190000h to 19ffffh 0c8000h to 0cffffh sa33 1 1 0 1 0 x x x 1a0000h to 1affffh 0d0000h to 0d7fffh sa34 1 1 0 1 1 x x x 1b0000h to 1bffffh 0d8000h to 0dffffh sa35 1 1 1 0 0 x x x 1c0000h to 1cffffh 0e0000h to 0e7fffh sa36 1 1 1 0 1 x x x 1d0000h to 1dffffh 0e8000h to 0effffh sa37 1 1 1 1 0 x x x 1e0000h to 1effffh 0f0000h to 0f7fffh sa38 1 1 1 1 1 x x x 1f0000h to 1fffffh 0f8000h to 0fffffh
mb84vd2108xem/2109xem -70 23 sector group addresses table (top boot block) sector group addresses table (bottom boot block) sector group a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 00000xxx sa0 sga1 00001xxx sa1 to sa3 00010xxx 00011xxx sga2 0 0 1xxxxxsa4 to sa7 sga3 0 1 0 x x x x x sa8 to sa11 sga4 0 1 1 x x x x x sa12 to sa15 sga5 1 0 0 x x x x x sa16 to sa19 sga6 1 0 1 x x x x x sa20 to sa23 sga7 1 1 0 x x x x x sa24 to sa27 sga8 11100xxx sa28 to sa30 11101xxx 11110xxx sga9 11111000 sa31 sga1011111001 sa32 sga1111111010 sa33 sga1211111011 sa34 sga1311111100 sa35 sga1411111101 sa36 sga1511111110 sa37 sga1611111111 sa38 sector group a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 00000000 sa0 sga1 00000001 sa1 sga2 00000010 sa2 sga3 00000011 sa3 sga4 00000100 sa4 sga5 00000101 sa5 sga6 00000110 sa6 sga7 00000111 sa7 sga8 00001xxx sa8 to sa10 00010xxx 00011xxx sga9 0 0 1 x x x x x sa11 to sa14 sga10 0 1 0 x x x x x sa15 to sa18 sga11 0 1 1 x x x x x sa19 to sa22 sga12 1 0 0 x x x x x sa23 to sa26 sga13 1 0 1 x x x x x sa27 to sa30 sga14 1 1 0 x x x x x sa31 to sa34 sga15 11100xxx sa35 to sa37 11101xxx 11110xxx sga16 1 1 1 1 1 x x x sa38
mb84vd2108xem/2109xem -70 24 flash memory autoselect codes table *1: a C1 is for byte mode. *2: output 01h at protected sector address and output 00h at unprotected sector address. type a 19 to a 12 a 6 a 1 a 0 a C1 * 1 code (hex) manufacturers code x v il v il v il v il 04h device code top boot block bank size=1 byte xv il v il v ih v il 36h word x 2236h bottom boot block bank size=1 byte xv il v il v ih v il 39 word x 2239h top boot block bank size=2 byte xv il v il v ih v il 2d word x 222dh bottom boot block bank size=2 byte xv il v il v ih v il 2e word x 222eh top boot block bank size=3 byte xv il v il v ih v il 28h word x 2228h bottom boot block bank size=3 byte xv il v il v ih v il 2bh word x 222bh top boot block bank size=4 byte xv il v il v ih v il 33h word x 2233h bottom boot block bank size=4 byte xv il v il v ih v il 35 word x 2235h sector group protect sector group address v il v ih v il v il 01h* 2
mb84vd2108xem/2109xem -70 25 flash memory command definitions table command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset * 1 1xxxhf0h read/reset * 1 word 3 555h aah 2aah 55h 555h f0h ra rd byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h (ba) 555h 90h byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0h pa pd byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h sector erase suspend 1 bab0h sector erase resume 1 ba30h set to fast mode word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program* 2 word 2 xxxh a0h pa pd byte reset from fast mode * 2 word 2 ba 90h xxxh f0h * 6 byte extended sector group protection * 3 word 4 xxxh 60h spa 60h spa 40h spa sd byte query * 4 word 1 55h 98h byte aah hiddenrom entry word 3 555h aah 2aah 55h 555h 88h byte aaah 555h aaah hiddenrom program * 5 word 4 555h aah 2aah 55h 555h a0h pa pd byte aaah 555h aaah hiddenrom erase * 5 word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h hra 30h byte aaah 555h aaah aaah 555h hiddenrom exit * 5 word 4 555h aah 2aah 55h (hrba) 555h 90h xxxh 00h byte aaah 555h (hrba) aaah
mb84vd2108xem/2109xem -70 26 *1: both read/reset commands are functionally equivalent, resetting the device to the read mode. *2: this command is valid while fast mode. *3: this command is valid while reset =v id . *4: the valid address is a 6 to a 0 . *5: this command is valid while hiddenrom mode. *6: the data 00h is also acceptable. notes : address bits a 19 to a 12 = x = h or l for all address commands except for program address (pa), sector address (sa), and bank address (ba). bus operations are defined in table 2 user bus operations. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 19 to a 15 ) spa = sector group address to be protected. set sector group address (sga) and (a 6 , a 1 , a 0 ) = (0, 1, 0). hra = address of the hiddenrom area. top boot block word mode : 0f8000h to 0fffffh byte mode : 1f0000h to 1fffffh bottom boot block word mode : 000000h to 007fffh byte mode : 000000h to 00ffffh hrba = bank address of the hiddenrom area. top boot block : a 15 = a 16 = a 17 = a 18 = a 19 = a 20 = 1 bottom boot block : a 15 = a 16 = a 17 = a 18 = a 19 = a 20 = 0 rd = data read from location ra during read operation. pd = data to be programmed at location pa. sd = sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. the system should generate the following address patterns; word mode : 555h or 2aah to addresses a 10 to a 0 byte mode : aaah or 555h to addresses a 10 to a 0 and a C1
mb84vd2108xem/2109xem -70 27 ? read only operations characteristics (flash) * : test conditions output load : 1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels : 0.0 v to 3.0 v timing measurement reference level input : 1.5 v output : 1.5 v parameter symbol test setup value* unit jedec standard min max read cycle time t avav t rc 70ns address to output delay t avqv t acc ce f = v il oe = v il 70ns chip enable to output delay t elqv t ce foe = v il 70ns output enable to output delay t glqv t oe 30 ns chip enable to output high-z t ehqz t df 25 ns output enable to output high-z t ghqz t df 25 ns output hold time from addresses, ce f or oe , whichever occurs first t axqx t oh 0ns reset pin low to read mode t ready 20 s
mb84vd2108xem/2109xem -70 28 ? read cycle (flash) we oe ce f t cef t oe dq address stable high-z output valid high-z t oeh t acc t rc reset t acc t oh dq t rc address stable high-z output valid t rh t df address address t rh t cef t rp ce f
mb84vd2108xem/2109xem -70 29 ? erase/program operations (flash) parameter symbol value unit jedec standard min typ max write cycle time t avav t wc 70 ns address setup time (we to addr.) t avwl t as 0ns address setup time to ce f low during toggle bit polling t aso 12 ns address hold time (we to addr.) t wlax t ah 45 ns address hold time from ce f or oe high during toggle bit polling t aht 0ns data setup time t dvwh t ds 30 ns data hold time t whdx t dh 0ns output enable setup time t oes 0ns output enable hold time read t oeh 0ns toggle and data polling 10 ns ce f high during toggle bit polling t ceph 20 ns oe high during toggle bit polling t oeph 20 ns read recover time before write (oe to ce f) t ghel t ghel 0ns read recover time before write (oe to we )t ghwl t ghwl 0ns we setup time (ce f to we )t wlel t ws 0ns cef setup time (we to ce f) t elwl t cs 0ns we hold time (ce f to we )t ehwh t wh 0ns cef hold time (we to ce f) t wheh t ch 0ns write pulse width t wlwh t wp 35 ns ce f pulse width t eleh t cp 35 ns write pulse width high t whwl t wph 25 ns cef pulse width high t ehel t cph 25 ns byte programming operation t whwh1 t whwh1 8 s word programming operation 16 s sector erase operation * 1 t whwh2 t whwh2 1 s v cc f setup time t vcs 50 s voltage transition time * 2 t vlht 4s rise time to v id * 2 t vidr 500 ns rise time to v acc t vaccr 500 ns recover time from ry/by t rb 0ns reset pulse width t rp 500 ns delay time from embedded output enable t eoe 70 ns reset hold time before read t rh 200 ns program/erase valid to ry/by delay t busy 90 ns erase time-out time * 3 t tow 50 s erase suspend transition time * 4 t spd 20 s
mb84vd2108xem/2109xem -70 30 *1 : this does not include the preprogramming time. *2 : this timing is for sector protection operation. *3 : the time between writes must be less than t tow otherwise that command will not be accepted and erasure will start. a time-out or t tow from the rising edge of last ce f or we whichever happens first will initiate the execution of the sector erase command(s). *4 : when the erase suspend command is written during the sector erase operation, the device will take a maximum of t spd to suspend the erase operation.
mb84vd2108xem/2109xem -70 31 ? write cycle (we control) (flash) t ch t wp t whwh1 t wc t ah ce f oe t rc dq t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t cef t ds d out address notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mb84vd2108xem/2109xem -70 32 ? write cycle (ce f control) (flash) notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode. (the addresses differ from 8 mode.) t cp t ds t whwh1 t wc t ah we oe dq t as t cph t dh dq 7 a0h d out ce f 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd address
mb84vd2108xem/2109xem -70 33 ? ac waveforms chip/sector erase operations (flash) address v cc f ce f oe dq we 555h 2aah 555h 555h 2aah sa *1 t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h/ 30h for sector erase 30h * : sa is the sector address for sector erase. addresses = 555h for chip erase. note : these waveform are for the 16 mode. (the addresses differ from 8 mode.)
mb84vd2108xem/2109xem -70 34 ? ac waveforms for data polling during embedded algorithm operations (flash) * : dq 7 = valid data (the device has completed the embedded operation.) t oeh t oe t whwh1 or 2 ce f oe we dq 7 t df t ch t cef dq 7 = valid data dq 7 * dq dq 6 to dq 0 = output flag t eoe dq 6 to dq 0 valid data high-z high-z (dq 6 to dq 0 ) data in data in t busy ry/by
mb84vd2108xem/2109xem -70 35 ? ac waveforms for toggle bit during embedded algorithm operations (flash) * : dq 6 stops toggling (the device has completed the embedded operation). address ry/by ce f we dq 6 /dq 2 oe t as t busy toggle t aht t aht t aso t oeh t oeh t oe data toggle data toggle data stop toggling data t cef * output valid t dh t ceph t oeph
mb84vd2108xem/2109xem -70 36 ? bank-to-bank read/write timing diagram (flash) cef dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address of bank 1. ba2: address of bank 2. ce f oe dq we address
mb84vd2108xem/2109xem -70 37 ?ry/by timing diagram during write/erase operations (flash) ? reset , ry/by timing diagram (flash) rising edge of the last write pulse ce f ry/by we t busy entire programming or erase operations t rp reset t ready ry/by we t rb
mb84vd2108xem/2109xem -70 38 ? temporary sector unprotection (flash) ? acceleration mode timing diagram (flash) reset v cc f ce f we ry/by t vlht program or erase command sequence t vlht t vcs t vidr v id t vlht unprotection period v ih v cc f v acc wp /acc v ih ce f we ry/by t vaccr t vlht t vcs t vlht t vlht acceleration mode period
mb84vd2108xem/2109xem -70 39 ? extended sector protection (flash) sgax : sector group address to be protected sgay : next group sector address to be protected time-out : time-out window = 250 m s (min) sgay reset a 6 oe we ce f data a 1 v cc f a 0 add sgax sgax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe t wp t wc t wc
mb84vd2108xem/2109xem -70 40 2. erase and programming performance (flash) parameter limit unit comment min typ max sector erase time 1 10 s excludes programming time prior to erasure byte programming time 8 300 m s excludes system-level overhead word programming time 16 360 m s excludes system-level overhead chip programming time 50 s excludes system-level overhead erase/program cycle 100,000 cycle
mb84vd2108xem/2109xem -70 41 n 2m sram characteristics for mcp 1. ac characteristics ? read cycle (sram) note: test conditions output load:1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to v cc s timing measurement reference level input: 0.5v cc s output: 0.5v cc s parameter symbol value unit min max read cycle time t rc 70 ns address access time t aa 70ns chip enable (ce1 s) access time t co1 70ns chip enable (ce2s) access time t co2 70ns output enable access time t oe 35ns lb , ub to output valid t ba 70ns chip enable (ce1 s low and ce2s high) to output active t coe 5ns output enable low to output active t oee 0ns ub , lb enable low to output active t be 0ns chip enable (ce1 s high or ce2s low) to output high-z t od 25ns output enable high to output high-z t odo 25ns ub , lb output enable to output high-z t bd 25ns output data hold time t oh 10 ns
mb84vd2108xem/2109xem -70 42 ?read cycle (sram) note : we remains h for the read cycle. t rc t aa t oh t co1 t od t odo t oee t coe valid data out address ce1 s oe dq ce2s t coe t oe t co2 t od lb , ub t ba t bd t be
mb84vd2108xem/2109xem -70 43 ? write cycle (sram) parameter symbol value unit min max write cycle time t wc 70 ns write pulse width t wp 50 ns chip enable to end of write t cw 55 ns address valid to end of write t aw 55 ns ub , lb to end of write t bw 55 ns address setup time t as 0ns write recovery time t wr 0ns we low to output high-z t odw 25 ns we high to output active t oew 0ns data setup time t ds 30 ns data hold time t dh 0ns
mb84vd2108xem/2109xem -70 44 ? write cycle * 3 (we control) (sram) t wc t as t wp t wr t cw t odw t oew t ds t dh valid data in address we ce1 s d out d in ce2s t cw *1 : if ce1 s goes l (or ce2s goes h) coincident with or after we goes l, the output will remain at high-z. *2 : if ce1 s goes h (or ce2s goes l) coincident with or before we goes h, the output will remain at high-z. *3 : if oe is h during the write cycle, the outputs will remain at high-z. *4 : because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. *1 *4 *2 *4 t bw lb , ub t aw
mb84vd2108xem/2109xem -70 45 ?write cycle * 1 (ce1 s control) (sram) t wc t as t wp t wr t cw t odw t coe t ds t dh valid data in address we ce1 s d out d in ce2s t cw *1 : if oe is h during the write cycle, the outputs will remain at high-z. *2 : because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. *2 lb , ub t bw t be t aw
mb84vd2108xem/2109xem -70 46 ?write cycle * 1 (ce2s control) (sram) t wc t as t wp t wr t cw t odw t coe t ds t dh valid data in address we ce1 s d out d in ce2s *1 : if oe is h during the write cycle, the outputs will remain at high-z. *2 : because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. *2 t cw lb , ub t bw t be t aw
mb84vd2108xem/2109xem -70 47 ?write cycle * 1 (lb , ub control) (sram) t wc t ds t dh address lb , ub we d in *1 : if oe is h during the write cycle, the outputs will remain at high-z. *2 : because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wp ce2s t cw ce1 s t as t wr t bw t odw t coe d out t be valid data in *2 t cw t aw
mb84vd2108xem/2109xem -70 48 2. data retention characteristics (sram) note : t rc : read cycle time ? ce1 s controlled data retention mode * 1 *1 : in ce1 s controlled data retention mode, input level of ce2s should be fixed vccs to vccsC0.2 v or vss to 0.2 v during data retention mode. other input and input/output pins can be used between C0.3 v to vccs+0.3 v. *2 : when ce1 s is operating at the v ih min level (2.2 v), the standby current is given by i sb1 s during the transition of v cc s from 3.3 v to 2.2 v. ? ce2s controlled data retention mode * * : in ce2s controlled data retention mode, input and input/output pins can be used between C0.3 v to vccs+0.3 v. parameter symbol value unit min typ max data retention supply voltage v dh 1.5 3.3 v standby current v dh = 1.5 v i dds2 1 4 m a chip deselect to data retention mode time t cdr 0ns recovery time t r t rc ns v cc s 2.7 v v ih gnd data retention mode *2 t cdr ce1 s v ccs C0.2 v *2 t r v dh v cc s 2.7 v gnd data retention mode v ih v il ce2s t cdr t r 0.2 v v dh
mb84vd2108xem/2109xem -70 49 n pin capacitance note : test conditions t a = + 25c, f = 1.0 mhz n handling of package please handle this package carefully since the sides of package create acute angles. n caution the high voltage (v id ) cannot apply to address pins and control pins except reset . exception is when autoselect and sector group protect function are used, then the high voltage (v id ) can be applied to reset . without the high voltage (v id ) , sector group protection can be achieved by using extended sector group protection command. parameter symbol test setup value unit typ max input capacitance c in v in = 0 11 14 pf output capacitance c out v out = 0 12 16 pf control pin capacitance c in2 v in = 0 14 16 pf wp /acc pin capacitance c in3 v in = 0 17 20 pf
mb84vd2108xem/2109xem -70 50 n ordering information mb84vd2108 device number/description 16mega-bit (2m 8-bit or 1m 16-bit) dual operation flash memory 3.0 v-only read, program, and erase 2mega-bit (256k 8-bit or 128k 16-bit) sram boot code sector architecture 84vd2108 = top sector 84vd2109 = bottom sector package type pbs = 56-ball bga em -70 pbs x speed option see product selector guide device revision (valid combination) em bank size 1 = 0.5mbit / 15.5mbit 2 = 2mbit / 14mbit 3 = 4mbit / 12mbit 4 = 8mbit / 8mbit
mb84vd2108xem/2109xem -70 51 n package dimension 56-pin plastic fbga (bga-56p-m02) dimensions in mm (inches) note : the values in parentheses are reference values. c 2002 fujitsu limited b56002s-c-1-1 7.20 0.10(.283 .004) 7.00 0.10 (.276 .004) index-mark area 0.39 0.10 (.015 .004) (stand off) .043 C.004 +.004 C0.10 +0.11 1.09 (mounting height) 0.40(.016) ref 0.40(.016) ref a b c d e f g h 1 2 3 4 5 6 7 8 56-?.018 C.002 +.004 C0.05 +0.10 56-?0.45 index b a 0.08(.003) m s a b 0.80(.031) ref 0.80(.031) ref s 0.10(.004) b s 0.20(.008) 0.20(.008) s a s
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